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Acer Aspire 8730, 8730Z

5 4 3 2 Big Bear 2 Block Diagram 3D3V_S5 23 SYSTEM DC/DC HOST BUS DDR2 DIMM1 TOP 667/800/1067MHz@1.05V AZALIA ALC888S VC 33 6 PCIe ports Giga LAN BCM5764MKMLG 28 TXFM PCIex1 PCIex1 Kedron a/b/g/n High Definition Audio PCIex1 LPC I/F OP AMP G1431Q 34 Matrix Storage Technology(DO) GFXCORE DC/DC 32 DCBATOUT 31 LPC BUS OP AMP G1412 34 Line Out (SPDIF) RJ11 36 19,20,21,22 USB Blue Tooth (USB) SPI 25 Camera (USB) 15 USB 4 Port 1st HDD SATA 24 2nd HDD SATA SATA A ODD SATA Touch Pad 36 INT. KB 36 INPUTS DEBUG CONN 37 DCBATOUT 0.7~1.25V B 42 OUTPUTS VCC_CORE_S0 0.35~1.5V CHARGER BQ24745 CIR INPUTS 36 47 OUTPUTS BT+ DCBATOUT 26 DCBATOUT CardReader Realtek 27 RTS5158E 24 LPC Launch Buttom 14 Finger Printer SATA BIOS/DASH 2Mb 37 MX25L16 W25X16 16M Bits37 WPC775 25 VGFXCORE CPU DC/DC KBC MODEM MDC Card OUTPUTS ISL6266A BIOS 35 46 INPUTS 32 Active Managemnet Technology(DO) INT.SPKR 2D5V_S0 ISL6263 Mini Card Kedron a/b/g/n Serial Peripheral I/F 44 3D3V_S0 Mini Card ETHERNET (10/100/1000MbE) C 29 PWR SW G577BR91U 31 12 USB 2.0/1.1 ports 35 1D5V_S0 G9131 RJ45 29 New card 4 SATA 44 1D8V_S3 30 PCIex1 ACPI 2.0 RT9018A MXM CONN PCI/PCI BRIDGE MIC In 44 DDR_VREF_S0 C-Link0 ICH9M Codec 1D8V_S3 DDR_VREF_S3 6,7,8,9,10,11 Line In RT9026 BOTTOM 18 PCIex16 X4 DMI 400MHz 35 S HDMI LVDS, CRT I/F 13 B 1D05V_S0 DCBATOUT GND INTEGRATED GRAHPICS 667/800MHz OUTPUTS 1D8V_S3 15 DDR Memory I/F INT.MIC 35 INPUTS 17 AGTL+ CPU I/F 45 TPS51124 VCC LCD Cantiga DDR2 DIMM2 35 CRT S 667/800MHz 12 C D PCB STACKUP 4, 5 667/800 MHz OUTPUTS THERMAL EMC2102 3 667/800 MHz 43 TPS51125 INPUTS DCBATOUT Penryn RTM875N-606-VD SYSTEM DC/DC Project code: 91.4AV01.001 PCB P/N : 48.4AV01. REVISION : -1 5V_S5 Mobile CPU CLK GEN. D 1 MS/MS Pro/xD /MMC/SD 5 in 1 A UMA Wistron Corporation 27 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title BLOCK DIAGRAM Size Custom Document Number Rev Date: Wednesday, October 22, 2008 5 4 3 2 -1 Big Bear 2 Sheet 1 1 of 50 A B C ICH9M Functional Strap Definitions Rev.1.5 ICH9 EDS 642879 D ICH9M Integrated Pull-up and Pull-down Resistors page 92 Signal HDA_SDOUT XOR Chain Entrance/ PCIE Port Config1 bit1, Rising Edge of PWROK Allows entrance to XOR Chain testing when TP3 pulled low.When TP3 not pulled low at rising edge of PWROK,sets bit1 of RPC.PC(Config Registers: offset 224h). This signal has weak internal pull-down CL_CLK[1:0] CL_DATA[1:0] PCIE config1 bit0, Rising Edge of PWROK. This signal has a weak internal pull-down. Sets bit0 of RPC.PC(Config Registers:Offset 224h) CL_RST0# PULL-UP 20K PCIE config2 bit2, Rising Edge of PWROK. DPRSLPVR/GPIO16 PULL-DOWN 20K GPIO20 Reserved This signal has a weak internal pull-up. Sets bit2 of RPC.PC2(Config Registers:Offset 0224h) This signal should not be pulled high. GNT1#/ GPIO51 ESI Strap (Server Only) Rising Edge of PWROK GNT0#: SPI_CS1#/ GPIO58 Top-Block Swap Override. Rising Edge of PWROK. Boot BIOS Destination Selection 0:1. Rising Edge of PWROK. Integrated TPM Enable, Rising Edge of CLPWROK ICH9 EDS 642879 SIGNAL ENERGY_DETECT PULL-DOWN 20K HDA_SDIN[3:0] PULL-DOWN 20K HDA_SDOUT PULL-DOWN 20K HDA_SYNC GNT[3:0]#/GPIO[55,53,51] PULL-DOWN 20K GPIO49 SATALED# SPKR TP3 GPIO33/ HDA_DOCK _EN# GPIO[49] PULL-UP 20K LDA[3:0]#/FHW[3:0]# PULL-UP 20K LDRQ[0] XOR Chain Entrance. Rising Edge of PWROK. Flash Descriptor Security Override Strap Rising