SS SISM760GX R367 TRAP3 TRAP4 130Ohm 1% C495 10uF/10V 2 C142 Z4XAVSS 2 0.1U C87 10uF/10V C124 0.1U 2 MuTIOL 2.0 Vref=0.25 *VCC1.8 ZVREF 2 1 1 R64 150Ohm 1% 1 0.01U 1 C131 0.1U 1 ON/1 OFF/0 Internal DISABLE ENABLE Pull Low R72 1 56Ohm 2 ZCMP_P Default Low/0 Pull Low Reserve TESTMODE1 A B ZCMP_N 2 C144 10uF/10V 56Ohm 2 MuTIOL 1.0 Vref=0.5 *VCC1.8 2 CPUCLK/ZCLK/AGPCLK PLL/DLL Circuit Enable TESTMODE0 DACAVSS Place near M760 chip. 1 SiS 760GX NB Hardware Trap Table DLLEN# C17 1U C19 0.1U R58 R65 49.9Ohm 1% 760GX VCOMP DACAVDD 2 0Ohm 1 C22 2 L5 120Ohm/100Mhz 1 2 Z4XAVDD 1 C132 1 1 0.01U Z1XAVSS 120Ohm/100Mhz 2 2 2 C134 2 1 1 2 0.1U 1 +1.8VS 2 R59 10KOhm VVBWN 1 V24 V29 R67 10KOhm /X C21 2 2 ENTEST DLLEN# MCLKAVSS C 1 TRAP0 TRAP1 TRAP2 TRAP3 TRAP4 0.1U 0.1U 1 R70 L28 1 Z1XAVDD 0.1U 0.01U 1 V25 U28 V26 V28 W25 W24 V27 U29 C48 +3.3VS +3.3VS L26 C135 MCLKAVDD C52 2 1 C119 10uF/10V +1.8VS +3.3VS 2 2 D9 C10 1 DCLKAVDD DCLKAVSS 1 DACAVDD DACAVSS DCLKAVSS +3.3VS L18 120Ohm/100Mhz 1 2 2 VGA (For 760 Only) A7 E10 TESTMODE0 TESTMODE1 TESTMODE2 PCIRST# C53 DACAVDD2 DACAVSS2 0.1U T16 T21 T20 1 1 1 VRSET PWROK F11 B7 E9 C44 0.01U 2 0.1U /X 2 C54 F10 PCI_RST# 1 PWROK 38 PWROK 13,16,25,30 PCI_RST# M760GX-3 DACAVDD1 DACAVSS1 DACAVDD DACAVSS MCLKAVDD MCLKAVSS MuTIOL VCOMP VRSET VVBWN C45 10uF/10V 2 ZAD0 ZAD1 ZAD2 ZAD3 ZAD4 ZAD5 ZAD6 ZAD7 ZAD8 ZAD9 ZAD10 ZAD11 ZAD12 ZAD13 ZAD14 ZAD15 ZAD16 C9 A10 B9 C43 1 AJ7 AG7 AE7 AD7 AG5 AF6 AJ4 AH4 AJ3 AG3 AF4 AE5 AE2 AF2 AE3 AF1 AG8 ZAD0 ZAD1 ZAD2 ZAD3 ZAD4 ZAD5 ZAD6 ZAD7 ZAD8 ZAD9 ZAD10 ZAD11 ZAD12 ZAD13 ZAD14 ZAD15 ZAD16 VCOMP VRSET VVBWN RSYNC LSYNC CSYNC 1 ZUREQ ZDREQ D7 F7 E8 CRT_RED 15 CRT_GREEN 15 CRT_BLUE 15 CRT_HSYNC 15 CRT_VSYNC 15 CRT_DDC2BD 15 CRT_DDC2BC 15 PCI_INTA# 13,16 2 ZVREF AE8 AF8 RSYNC LSYNC CSYNC R12 1 R13 1 R10 1 R9 1 2 AD5 ZUREQ ZDREQ B8 A8 A9 D8 F9 C7 C8 F8 1 ZCOMP_N ZCOMP_P CRT_RED CRT_GREEN CRT_BLUE 2 33Ohm CRT_HSYNC 2 33Ohm CRT_VSYNC 2 100Ohm CRT_DDC2BD 2 100Ohm CRT_DDC2BC PCI_INTA# ROUT GOUT BOUT HSYNC VSYNC VGPIO1 VGPIO0 INTA# 2 AD6 AC6 The differences between the traces of MuTIOL Strobes and Data should be smaller than 0.05" 120Ohm/100Mhz D DCLKAVDD 2 Z1XAVDD Z1XAVSS Z4XAVDD Z4XAVSS ZAD[0..16] 1 1 +3.3VS L15 120Ohm/100Mhz 1 2 CLK_14_NB 19 1 AB1 AB2 AD3 AD4 CLK_14_NB B10 1 ZSTB1 ZSTB#1 VOSCI 1 AG1 AH2 ZVREF B 2 2 ZSTB0 ZSTB#0 ZCMP_N ZCMP_P 16 ZAD[0..16] AJ5 AH6 Z1XAVDD Z1XAVSS Z4XAVDD Z4XAVSS 16 ZUREQ 16 ZDREQ ZCLK ZSTB1 ZSTB1# 16 ZSTB1 16 ZSTB1# AE1 ZSTB0 ZSTB0# 16 ZSTB0 16 ZSTB0# C 4 U42C CLK_ZIP_NB 19 CLK_ZIP_NB 2 D 7 Control & Hardware Trap 8 755 Test Mode Selection 1: Mode1 0: MOde0 Pull Low Low/0 TESTMODE2 755 Test Mode Enable ENABLE DISABLE Pull Low Low/0 TRAP0 MuTIOL Verision 1 , 2 Ver. 1 Ver. 2 Pull Low Low/0 DISABLE ENABLE Pull Low Low/0 DISABLE Frequence < 100MHz ENABLE Normal Mode (200MHz) Pull Low Low/0 Pull Low Low/0 Pull Low High/1 A +3.3VS TRAP1 TRAP2 TRAP3 TRAP4 MuTIOL DBI Mode MuTIOLIntial Packet Series Mode PLL 1X Gain Control Reserve /X /X RSYNC CSYNC LSYNC R17 R19 R28 1 1 1 2 2 2 4.7KOhm 4.7KOhm 4.7KOhm R16 R18 /X