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BENQ Joybook U102

VSS NC/CKE1 VDD NC/A15 NC/A14 VDD A11 A7 A6 VDD A4 A2 A0 VDD BA1 RAS# S0# VDD ODT0 NC/A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1# VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS SA0 SA1 GND DDR_A_D4 DDR_A_D5 DDR_A_DM0 DDR_A_D6 DDR_A_D7 DDR_A_D12 DDR_A_D13 D DDR_A_DM1 M_CLK_DDR0 M_CLK_DDR#0 M_CLK_DDR0 <6> M_CLK_DDR#0 <6> DDR_A_D14 DDR_A_D15 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 DDR_A_D20 DDR_A_D21 R59 R59 DDR_A_DM2 1 2 0_0402_5% PM_EXTTS#0 <6> DDR_A_D22 DDR_A_D23 DDR_A_D28 DDR_A_D29 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_D30 DDR_A_D31 DDR_CKE1 DDR_CKE1 <6> C DDR_A_MA11 DDR_A_MA7 DDR_A_MA6 DDR_A_MA4 DDR_A_MA2 DDR_A_MA0 DDR_A_BS1 DDR_A_RAS# DDR_CS0# DDR_A_BS1 <7> DDR_A_RAS# <7> DDR_CS0# <6> M_ODT0 DDR_A_MA13 M_ODT0 <6> DDR_A_D36 DDR_A_D37 DDR_A_DM4 DDR_A_D38 DDR_A_D39 DDR_A_D44 DDR_A_D45 DDR_A_DQS#5 DDR_A_DQS5 B DDR_A_D46 DDR_A_D47 DDR_A_D52 DDR_A_D53 M_CLK_DDR1 M_CLK_DDR#1 M_CLK_DDR1 <6> M_CLK_DDR#1 <6> DDR_A_DM6 DDR_A_D54 DDR_A_D55 DDR_A_D60 DDR_A_D61 DDR_A_DQS#7 DDR_A_DQS7 DDR_A_D62 DDR_A_D63 R326 R326 1 R325 R325 1 2 10K_0402_5% 2 10K_0402_5% A DIMMA Compal Electronics, Inc. Compal Secret Data 2006/08/18 2008/09/20 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 3 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 FOX_AS0A426-N4SN-7F CONN@ Security Classification Issued Date CLK_SMBDATA CLK_SMBCLK +3VS 0.1U_0402_16V4Z RP6 RP6 M_ODT0 DDR_A_MA0 DDR_A_RAS# DDR_A_BS1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 Title DDRII-SODIMMA Size B Date: Document Number Rev 1.0 KTV00 LA-5241P Thursday, May 07, 2009 Sheet 1 11 of 39 5 4 3 2 1 +3VS +3VM_CK505 FSC FSB FSA CLKSEL2 CLKSEL1 CLKSEL0 CPU MHz SRC MHz PCI MHz REF MHz DOT_96 USB MHz MHz 0 0 0 266 100 33.3 14.318 96.0 48.0 C240 47P_0402_50V8J 0 0 1 133 100 33.3 14.318 96.0 48.0 Close to L11 0 1 0 200 100 33.3 14.318 96.0 48.0 0 1 1 166 100 33.3 14.318 96.0 48.0 1 0 0 333 100 33.3 14.318 96.0 48.0 1 0 1 100 100 33.3 14.318 96.0 48.0 1 1 0 400 100 33.3 14.318 96.0 48.0 1 1 1 L15 1 L15 +3VS <EMI> 2 FBMA-L11-160808-121LMT_0603 1 1 1 C237 C237 1 C210 C210 1 C234 C234 1 C238 C238 1 C239 C239 1 C235 C235 R239 R239 2 2 10U_0805_10V4Z 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 R238 1 1 C204 47P_0402_50V8J 1 1 C198 C198 1 C214 C214 C208 C208 1 1 C206 C206 1 C217 C217 1 C221 C221 C228 C228 <17> ICH_SMBDATA CLK_SMBDATA Q4A Q4A 2 <RF> 2 10U_0805_10V4Z 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z D +3VS 5 Close to L12 L15 0_0402_5% 2 @ 2N7002DW-T/R7_SOT363-6 6 1 2 +VCCP 2.2K_0402_5% 0.1U_0402_16V4Z +1.05VM_CK505 <EMI> 2 1 L14 FBMA-L11-160808-121LMT_0603 D R225 R225 C218 C218 2.2K_0402_5% <RF> Q4B Q4B 4 3 <17> ICH_SMBCLK L14 CLK_SMBCLK 2N7002DW-T/R7_SOT363-6 0_0603_5% @ R226 1 SA000020K00 (Silego : SLG8SP556VTR ) SA000020H10 (ICS : ICS9LPRS387AKLFT) Reserved 0_0603_5% @ 2 @ 0_0402_5% SRC PORT LIST +VCCP 2 0118 change L14 & L15