Платформа установлена в:

BENQ Joybook U102

to 0_0603 +3VM_CK505 @ 1 2 R208 0_0402_5% 56_0402_5% 1 R174 2 MCH_CLKSEL0 <6> VDD_PCI VDD_CPU 19 0120 Add C403 for noise Change C403 from 100p to 330p 0319 VDD_48 SRC_0#/DOT_96# 25 CLK_MCH_DREFCLK# VDD_SRC_IO VDD_SRC_IO 12_0402_5% 1 LCDCLK/27M <17> CLK_ICH_48M R202 2 R202 1 20 2 7 REF_1 2 EMI 1 <RF> @ MCH_CLKSEL2 <6> 1 R233 R233 1K_0402_5% R236 R236 H_STP_CPU# <17> H_STP_CPU# CLK_ICH_48M 33P_0402_50V8J H_STP_PCI#_R <17> H_STP_PCI#_R C242 C242 CLK_ICH_14M 2 1 10P_0402_50V8J C246 CLK_PCI_LPC <RF> @ 33P_0402_50V8J C247 CLK_PCI_ICH <RF> @ 33P_0402_50V8J 33_0402_5% 1 R219 2 R219 33_0402_5% 1 53 R220 2 R220 C426 close to U12 : : : : +3VS A R227 R232 R229 10K_0402_5% @ 10K_0402_5% @ PCI4_SEL ITP_EN 54 PCI_STOP# 1 1 1 1 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 4 PCI_1 PCI_2 C398 100P_0402_50V8J B SRC_9 44 SRC_9# 1 CLK_PCIE_LAN 45 CLK_PCIE_LAN# SRC_10 50 CLK_PCIE_LAN# <24> CLK_PCIE_ICH 51 CLK_PCIE_LAN <24> CLK_PCIE_ICH# CLK_PCIE_ICH CLK_PCIE_ICH# 2 <17> C425 100P_0402_50V8J C425 靠近U12 <17> PCIF_5/ITP_EN 3 2 SATA_CLKREQ# SRC_10# VSS_PCI 1 C393 C393 220P_0402_50V7K 0210 Add C425 for power noise PCI_4/SEL_LCDCL 17 MCH_CLKREQ# 1 2 63 PCI_3 16 LAN_CLKREQ# CLK_PCIE_WLAN# <19> 60 XTAL_OUT 14 CLK_PCIE_WLAN <19> 64 XTAL_IN VSS_REF 22 VSS_48 47 CLKREQ_3# 37 REQ PORT LIST 48 SRC_11# PORT 26 VSS_IO CLKREQ_4# 69 VSS_CPU CLKREQ_6# 58 30 VSS_PLL3 CLKREQ_7# CLKREQ_9# 43 VSS_SRC SLKREQ_10# CLKREQ_11# 46 73 VSS USB_1/CLKREQ_A# 21 WLAN_CLKREQ# WLAN_CLKREQ# <19> LAN_CLKREQ# LAN_CLKREQ# <24> SATA_CLKREQ# DEVICE REQ_3# REQ_4# REQ_6# REQ_7# REQ_9# REQ_10# REQ_11# REQ_A# 49 VSS_SRC MCH_CLKREQ# <6> 65 VSS_SRC MCH_CLKREQ# 41 @ R230 10K_0402_5% SATA_CLKREQ# <17> MCH_3GPLL PCIE_WLAN PCIE_LAN A SATA Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 1 10K_0402_5% 1 1 R231 R231 10K_0402_5% 4 2 2 2 2 SLG8SP556VTR_QFN72_10X10 R228 R228 Routing the trace at least 10mil R259 R259 R181 R181 R212 R186 R186 PCI2_TME 2 2 2 CLK_XTAL_OUT PCI4_SEL 2 ITP_EN 27P_0402_50V8J LAN_CLKREQ# MCH_CLKREQ# SATA_CLKREQ# WLAN_CLKREQ# CLK_MCH_3GPLL# <8> 61 SRC_8/CPU_ITP 5 1 1 1 1 Y1 Y1 CLK_MCH_3GPLL <8> 10K_0402_5% CLK_XTAL_IN 14.31818MHZ X5H01431AFG1H-X +3VS CLK_PCIE_SATA# <16> CLK_PCIE_WLAN# 42 +3VS 2 2 Change Y2 value from 14.31818MHZ X5H01431AFG1H-X to 14.31818MHZ X5H01431AFG1H-X 2 +3VS Change Y2 footprint from Y_6X1430004201_2P to Y_7A14300083_2P CLK_PCIE_SATA <16> CLK_PCIE_WLAN 59 Change Y2 part number from SJ114P3M720 to SJ100003B00 27P_0402_50V8J 57 34 For PCI2_TME:0=Overclocking of CPU and SRC allowed (ICS only) 1=Overclocking of CPU and SRC NOT allowed <6> C PCIE_LAN PCIE_ICH 0120 Add C393 C398 for power noise Change C393 from 100p to 220p 0319. 56 SRC_11 DOT96 / DOT96# LCDCLK / LCDCLK# SRC_0 / SRC_0# 27M/27M_SS <6> MCH_SSCDREFCLK# PCIE_WLAN 39 SRC_7 For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP# For PCI4_SEL, 0 = Pin24/25 Pin28/29 1 = Pin24/25 Pin28/29 MCH_SSCDREFCLK <6> 40 CPU_STOP# 18 <15> CLK_PCI_ICH C426 100P_0402_50V8J SRC_4 SRC_6 NC 15 H_STP_PCI#_R CLK_MCH_3GPLL# CLK_MCH_DREFCLK# MCH_DREFCLK SATA HDD MCH_3GPLL CKPWRGD/PD# 13 <25> CLK_PCI_LPC 1 CLK_MCH_3GPLL SRC_8#/CPU_ITP# CLK_XTAL_OUT PCI2_TME 0211 Add C426 for power noise 35 36 SRC_7# CLK_XTAL_IN 2 0_0402_5% CLK_PCIE_SATA# SRC_6# C233 1K_0402_5% @ 1 2 33 SRC_4# 1 CLK_SD_48M 33P_0402_50V8J <RF> @ CLK_PCIE_SATA USB_0/FS_A 11 C222 2 R234 R234 32 <6> REF_0/FS_C/TEST_ VGATE <17,25,37> VGATE SRC_2 FS_B/TEST_MODE FSC R217 2 R217 MCH_SSCDREFCLK# SRC_3 FSA 8 33_0402_5% 1 <17> CLK_ICH_14M MCH_SSCDREFCLK SRC_3# VDD_SRC_IO 28 29 CLK_MCH_DREFCLK DEVICE VDD_IO R196