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BENQ Joybook U102

2 R196 12_0402_5% 1 +VCCP 5 CLK_MCH_BCLK# <6> LCDCLK#/27M_SS 2 <23> CLK_SD_48M 0_0402_5% C243 C243 CLK_MCH_BCLK <6> VDD_PLL3_IO FSB C244 C244 67 CLK_CPU_BCLK# <4> SRC_2# 1 MCH_CLKSEL1 <6> R214 R214 1K_0402_5% 2 CPU_1# CLK_MCH_BCLK# CLK_MCH_DREFCLK 38 2 N270@ B CLK_MCH_BCLK 24 23 R215 @ 1 2 R235 0_0402_5% 68 SRC_0/DOT_96 62 1K_0402_5% FSC CPU_1 CLK_CPU_BCLK <4> 31 C403 C403 330P_0402_50V7K N280@ <4> CPU_BSEL2 CPU_0# CLK_CPU_BCLK# VDD_CPU_IO 52 2 R237 R237 10K_0402_5% 2 1 CLK_CPU_BCLK 66 R213 @ 1 2 R216 0_0402_5% 71 70 VDD_PLL3 1 +VCCP <4> CPU_BSEL1 CPU_0 PORT SRC0 SRC2 SRC3 SRC4 SRC6 SRC7 SRC8 SRC9 SRC10 SRC11 CLK_SMBDATA <11> CLK_SMBCLK <11> VGATE +1.05VM_CK505 1 CLK_SMBCLK 27 1K_0402_5% @ C FSB CLK_SMBDATA 10 VDD_REF 72 R205 9 SCL VDD_SRC 6 R218 R218 1K_0402_5% 2 SDA 55 H_STP_PCI#_R 2 @ 10K_0402_5% 12 1 1 1 <4> CPU_BSEL0 U12 U12 +3VS R222 R222 R203 R203 2.2K_0402_5% FSA 2 1 2007/10/15 Deciphered Date 2008/09/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 3 2 Title Clock Generator CK505 Size Document Number Rev 1.0 KTV00 LA-5241P Date: Thursday, May 07, 2009 Sheet 1 12 of 39 5 4 3 2 1 LCD POWER CIRCUIT +LCDVDD +3VS +3VALW 1 W=20mils R283 R283 150_0603_5% 3 3 2 Q15 AO3413_SOT23-3 2 1 1 47K_0402_5% 2 6 0.1U_0402_16V4Z W=20mils Q16A Q16A 2 1 C413 100P_0402_50V8J 1 @ 2N7002DW-T/R7_SOT363-6 1 GMCH_ENVDD R281 R281 100K_0402_5% 1 2 <8> GMCH_ENVDD 2 C293 C293 +LCDVDD 1 0210 Add C413 for noise PJDLC05_SOT23-3 1 32 2 R287 R287 4 5 G 2N7002DW-T/R7_SOT363-6 0118 Remove C305 4.7u 0805 D19 D19 D D Q16B Q16B 2 1 D R286 R286 47K_0402_5% S S D 1 C294 4.7U_0805_10V4Z 2 2 C298 C298 0.1U_0402_16V4Z 靠近 Q16 C C C295 @ 0.1U_0402_16V4Z 1 2 <EMI> C296 C296 330P_0402_50V7K 1 2 +LEDVDD C297 C297 1 LED PANEL/CMOS. Conn. 100P_0402_50V8J 2 JLVDS1 LVDS_ACLK# LVDS_ACLK 0120 Add C395 for noise <8> <8> INVT_PWM <8> <8> 1 B 2 C395 100P_0402_50V8J <8> <8> LVDS_A2# LVDS_A2 LVDS_A2# LVDS_A2 LVDS_A0# LVDS_A0 LVDS_A0# LVDS_A0 LVDS_A1# LVDS_A1 LVDS_A1# LVDS_A1 LVDS_SDA LVDS_SCL LVDS_PWM 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 31 <8> LVDS_ACLK# <8> LVDS_ACLK GNDGND 32 0210 Add C409 for noise BKOFF# 400mA +LEDVDD L17 L17 +LCDVDD_L 1 2 FBMA-L11-201209-221LMA30T_0805 B+ L16 L16 1 2 FBMA-L11-201209-221LMA30T_0805 +LCDVDD +3VS +3VS 280mA 40MIL For panel ADJ 1 USB20_P1_1 USB20_N1_1 BKOFF# C1 C1 0.1U_0402_16V4Z 2 1 @ <EMI> 2 B C299 0.1U_0402_16V4Z BKOFF# <25> ACES_88242-3001 1 C409 C409 220P_0402_50V7K 2 1 靠近 JLVDS1 Change C409 from 100p to 220p; 0319 R285 R285 10K_0402_5% +3VS R284 R284 10K_0402_5% 1 2 2 <25> INVT_PWM A <8> L_BKLTCTL INVT_PWM L_BKLTCTL @ 1 0_0402_5% 1 0_0402_5% 2 USB20_N1 1 USB20_P1 4 0_0402_5% @ 1 2 2 USB20_N1_1 4 3 3 USB20_P1_1 LVDS_SCL <8> LVDS_SDA 2 R346 R346 2 R345 1 L20 <17> USB20_N1 LVDS_SCL Option panel brightness control R302 R302 LVDS_SDA <8> <17> USB20_P1 WCM2012F2S-900T04_0805 LVDS_PWM R303 R303 1 2 A 0_0402_5% Change USB20_N1 and USB20_P1 01/06 2006/08/18 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2008/09/20 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY