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BENQ Joybook U102

LOW HIGH HIGH ON ON OFF OFF S4 (Suspend to Disk) LOW LOW HIGH ON OFF OFF OFF S5 (Soft OFF) 3 Address Smart Battery SIGNAL Device LOW LOW LOW ON OFF OFF OFF 3 ICH7M SM Bus address BOARD ID Table(Page 25) ID 0 1 2 3 BRD ID R01 (EVT) R02 (DVT) R03 (PVT) R10A (MP) Ra NC 100K 100K 100K Device Rb 0 8.2K 18K NC 0V 0.25V 0.50V 3.3V 1101 001Xb DDR DIMMA Vab Address Clock Generator (SLG8SP556VTR) 1010 000Xb 4 4 Compal Electronics, Inc. Compal Secret Data Security Classification 2006/08/18 Issued Date Deciphered Date 2008/09/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title Notes List Size Document Number Custom Date: Thursday, May 07, 2009 Rev 1.0 KTV00 LA-5241P Sheet E 3 of 39 5 4 3 1 <16> H_A20M# <16> H_FERR# <16> H_IGNNE# <16> H_STPCLK# <16> H_INTR <16> H_NMI <16> H_SMI# LOCK# W20 H_LOCK# D15 W18 Y17 U20 W19 H_RESET# H_RS#0 H_RS#1 H_RS#2 H_TRDY# AA17 V20 H_HIT# H_HITM# CONTROL HIT# HITM# N280@ <6> R51 R51 1 2 1K_0402_5% H_LOCK# <6> H_INIT# <16> Close to CPU H_RESET# <6> H_RS#[0..2] <6> <6> H_DSTBN#0 <6> H_DSTBP#0 <6> H_DINV#0 H_TRDY# <6> <6> H_D#[16..31] H_HIT# <6> H_HITM# <6> BPM[0]# BPM[1]# BPM[2]# BPM[3]# PRDY# PREQ# TCK TDI TDO TMS TRST# BR1# K17 J18 H15 J15 K18 J16 M17 N16 M16 L17 K16 V15 PROCHOT# THRMDA THRMDC G17 E4 E5 H_PROCHOT#_R H_THERMDA H_THERMDC THERMTRIP# H17 H_THERMTRIP# PREQ# ITP_TCK ITP_TDI ITP_TDO ITP_TMS ITP_TRST# 1 R314 R314 2 22_0402_5% VR_TT# <37> <6> H_DSTBN#1 <6> H_DSTBP#1 <6> H_DINV#1 Close to CPU @ T7 H_THERMTRIP# <6,16> +CPU_GTLREF V11 V12 BCLK[0] BCLK[1] @ T5 PAD CLK_CPU_BCLK CLK_CPU_BCLK# R47 R48 @ @ 1 1 Y11 W10 Y12 AA14 AA11 W12 AA16 Y10 Y9 Y13 W15 AA13 Y16 W13 AA9 W9 Y14 Y15 W16 V9 D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]# DP#0 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_DSTBN#1 H_DSTBP#1 H_DINV#1 H_DP#1 AU80586GF028512 _FCBGA437 H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_DSTBN#0 H_DSTBP#0 H_DINV#0 H_DP#0 AA5 Y8 W3 U1 W7 W6 Y7 AA6 Y3 W2 V3 U2 T3 AA8 V2 W4 Y4 Y5 Y6 R4 D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]# DP#1 A7 U5 V5 T17 R6 M6 N15 N6 P17 T6 J6 H5 G5 GTLREF ACLKPH DCLKPH BINIT# MISC EDM EXTBGREF FORCEPR# HFPLL MCERR# RSP# BSEL[0] BSEL[1] BSEL[2] PAD 2 1K_0402_5% 2 1K_0402_5% ACLKPH DCLKPH CLK_CPU_BCLK <12> CLK_CPU_BCLK# <12> +CPU_EXTBGREF C21 C1 A3 RSVD3 RSVD2 RSVD1 CPU_BSEL0 CPU_BSEL1 CPU_BSEL2 <12> CPU_BSEL0 <12> CPU_BSEL1 <12> CPU_BSEL2 ITP_TMS ITP_TDI PREQ# ITP_TDO VR_TT# 1 1 2 <BOM Structure> Close to CPU pin within 500mils. Zo=55ohm C68 1U_0402_6.3V4Z H_DSTBN#3 <6> H_DSTBP#3 <6> H_DINV#3 <6> 2 2 1 1 H_DPRSTP# H_DPSLP# H_DPWR# H_PWRGOOD H_CPUSLP# R18 R17 U4 V17 N18 A13 B7 <6> 27.4_0402_1% 54.9_0402_1% 27.4_0402_1% 54.9_0402_1% C H_DPRSTP# <16,37> H_DPSLP# <16> H_DPWR# <6> H_PWRGOOD <16> H_CPUSLP# <6> +CPU_CMREF Zo=27.4ohm +/-15%, make than 0.5" Zo=55ohm +/-15%, make than0.5" 1 R41 R41 2K_0402_1% 2 C69 0.1U_0402_16V4Z 2 R36 R36 2K_0402_1% 2 2 56_0402_5% 2 56_0402_5% @ 2 56_0402_5% 2 56_0402_5% 2 68_0402_5% @ T