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Acer Aspire 8730, 8730Z

Edge of PWROK LDRQ[1]/GPIO23 PULL-UP 20K Signal has weak internal pull-up. Sets bit 27 of MPC.LR(Device 28:Function 0:Offset D8) PWRBTN# SATALED# SPI_CS1#/GPIO58/CLGPIO6 PULL-DOWN 20K SPI_MISO SPKR PULL-DOWN 20K LANE3 MiniCard WWAN/TV LANE4 JMB385 Card Reader LANE5 NewCard LANE6 NC 0 = Reverse Lanes,15->0,14->1 ect.. 1= Normal operation(Default):Lane Numbered in order CFG10 PCIE Loopback enable 0 = Enable (Note 3) 1= Disabled (default) TP[3] PULL-UP 20K USB[11:0][P,N] 00 10 01 11 PULL-UP 20K = = = = Reserve XOR mode Enabled ALLZ mode Enabled (Note 3) Disabled (default) PULL-DOWN 15K Sampled low:the Flash Descriptor Security will be overridden. If high,the security measures will be in effect.This should only be enabled in manufacturing environments using an external pull-up resister. USB MiniCard WLAN PCIE Graphics Lane PULL-UP 20K This signal should not be pull low unless using XOR Chain testing. USB Table LAN MARVELL 88E8071 0 = Transport Layer Security (TLS) cipher suite with no confidentiality 1 = TLS cipher suite with confidentiality (default) CFG9 PULL-UP 20K SPI_MOSI Media Board SMBC_Therm SMBD_Therm LANE2 0 = DMI x2 1 = DMI x4 (Default) 0= The iTPM Host Interface is enabled(Note2) 1=The iTPM Host Interface is disalbed(default) Intel Management engine Crypto strap PULL-UP 15K If sampled high, the system is strapped to the "No Reboot" mode(ICH9 will disable the TCO Timer system reboot feature). The status is readable via the NO REBOOT bit. 4 CFG7 PULL-UP 20K SMBus LANE1 iTPM Host Interface PULL-UP 20K 2 PCIE Routing DMI x2 Select PULL-UP 20K DMI Termination Voltage, The signal is required to be low for desktop Rising Edge of PWROK. applications and required to be high for mobile applications. PCI Express Lane Reversal. Rising Edge of PWROK. No Reboot. Rising Edge of PWROK. CFG5 PULL-UP 20K LAN_RXD[2:0] Configuration Reserved PULL-UP 20K GPIO[20] 0.5 000 = FSB1067 011 = FSB667 010 = FSB800 others = Reserved PULL-DOWN 20K TACH_[3:0] 3 Strap Description FSB Frequency Select CFG6 The pull-up or pull-down active when configured for native GLAN_DOCK# functionality and determined by LAN controller GLAN_DOCK# Controllable via Boot BIOS Destination bit (Config Registers:Offset 3410h:bit 11:10). GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC. Sample low: the Integrated TPM will be disabled. Sample high: the MCH TPM enable strap is sampled low and the TPM Disable bit is clear, the Integrated TPM will be enable. CFG[4:3] CFG8 CFG[15:14] CFG[18:17] PULL-UP 20K HDA_RST# CFG[2:0] PULL-DOWN 20K HDA_DOCK_EN#/GPIO33 Sampled low:Top-Block Swap mode(inverts A16 for all cycles targeting FWH BIOS space). Note: Software will not be able to clear the Top-Swap bit until the system is rebooted without GNT3# being pulled down. Pin Name PULL-UP 20K HDA_BIT_CLK ESI compatible mode is for server platforms only. This signal should not be pulled low for desttop and mobile. Rev.1.5 Resistor Type/Value PME# SPI_MOSI 1 page 218 PULL-UP 20K HDA_SYNC GNT3#/ GPIO55 Comment Montevina Platform Design guide 22339 PULL-UP 20K GNT2#/ GPIO53 4 Usage/When Sampled E Cantiga chipset and ICH9M I/O controller Hub strapping configuration Pair KBC CFG[13:12] CFG16 CFG19 XOR/ALL FSB Dynamic ODT DMI Lane Reversal 3 0 = Dynamic ODT Disabled 1 = Dynamic ODT Enabled (Default) 0 = Normal operation(Default): Lane Numbered in Order 1 = Reverse Lanes DMI x4 mode[MCH -> ICH]:(3->0,2->1,1->2and0->3) DMI x2 mode[MCH -> ICH]:(3->0,