Платформа установлена в:

BENQ Joybook U102

6 R46 R46 R45 R45 R13 R13 R5 R5 H_D#[48..63] R39 R39 1K_0402_1% +CPU_CMREF 1 1 C67 0.1U_0402_16V4Z R37 R37 1K_0402_1% +CPU_EXTBGREF 1 1K_0402_5% H_A20M# 1K_0402_5% H_IGNNE# This shall place near CPU 1 1 1 1 1 H_DSTBN#2 <6> H_DSTBP#2 <6> H_DINV#2 <6> @ T8 2 R38 R38 1K_0402_1% +CPU_GTLREF +VCCP R11 R11 R7 R7 R12 R8 R8 R313 R313 DPRSTP# DPSLP# DPWR# PWRGOOD SLP# CORE_DET CMREF[1] T1 T2 F20 F21 D 1 2 2 1 1 1 H_A#32 H_A#33 H_A#34 H_A#35 +VCCP B COMP[0] COMP[1] COMP[2] COMP[3] Layout note: COMP0,2 connect with trace length shorter COMP1,3 connect with trace length shorter +VCCP 2 R6 R6 R42 R42 1K_0402_5% 1K_0402_5% 1K_0402_5% 1K_0402_5% +VCCP 1 2 2 2 2 +VCCP 2 1 1 1 1 C2 G2 F1 D3 B4 E1 A5 C3 A6 F2 C6 B6 B3 C4 C7 D2 E2 F3 C5 D4 <6> B R40 R40 2K_0402_1% 2 2 . N270@ R304 R304 R307 R307 R305 R305 R312 R312 D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]# DSTBN[3]# DSTBP[3]# DINV[3]# DP#3 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_DSTBN#2 H_DSTBP#2 H_DINV#2 H_DP#2 PAD H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DSTBN#3 H_DSTBP#3 H_DINV#3 H_DP#3 PAD COMP0 1 COMP1 1 COMP2 2 COMP3 2 R3 R2 P1 N1 M2 P2 J3 N3 G3 H2 N2 L2 M3 J2 H1 J1 K2 K3 L1 M4 AU80586GE025512_FCBGA437 N270@ AU80586GE025512_FCBGA437 +VCCP D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# DSTBN[2]# DSTBP[2]# DINV[2]# DP#2 DATA GRP 2 H_IERR# H_INIT#_R H_BR0# R50 R50 330_0402_5% H_D#[32..47] U19B 1 F16 V16 1 NC1 NC2 NC3 NC4 NC5 NC6 NC7 IERR# INIT# 2 A20M# FERR# IGNNE# STPCLK# LINT0 LINT1 SMI# H_BR0# RESET# RS[0]# RS[1]# RS[2]# TRDY# THERM XDP/ITP SIGNALS U18 T16 J4 R16 T15 R15 U17 PAD T20 R31 R31 56_0402_5% H_DEFER# <6> H_DRDY# <6> H_DBSY# <6> <6> H_D#[0..15] U19 +VCCP H CLK @ T3 H_DEFER# H_DRDY# H_DBSY# BR0# NC H_A20M# H_FERR# H_IGNNE# H_STPCLK# H_INTR H_NMI H_SMI# H_ADSTB#1 A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# ADSTB[1]# AP1 T21 T19 Y18 +VCCP H_ADS# <6> H_BNR# <6> H_BPRI# <6> DATA GRP 1 DATA GRP 1 <6> C19 F19 E21 A16 D19 C14 C18 C20 E20 D20 B18 C15 B16 B17 C16 A17 B14 B15 A14 B19 M18 H_ADS# H_BNR# H_BPRI# DEFER# DRDY# DBSY# ADDR GROUP 1 ADDR GROUP 1 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 H_ADSTB#1 H_AP1 <6> H_A#[17..31] V19 Y19 U21 ADDR GROUP 0 <6> H_ADSTB#0 <6> H_REQ#[0..4] ADS# BNR# BPRI# A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]# AP0 REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]# D6 G6 H6 K4 K5 M15 L16 D P21 H20 N20 R20 J19 N19 G20 M19 H21 L20 M20 K19 J20 L21 K20 D17 N21 J21 G19 P20 R19 DATA GRP 0 DATA GRP 0 H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_ADSTB#0 @ T4 H_AP0 PAD H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 DATA GRP 3 U19A C 2 H_A#[3..16] 2 <6> <BOM Structure> Close to CPU pin within 500mils. Zo=55ohm <BOM Structure> Close to CPU pin within 500mils. Zo=55ohm H_THERMDA, H_THERMDC routing together. Trace width / Spacing = 10 / 10 mil Modify schematic by 10/21 1 1 2 56_0402_5% 2 56_0402_5% +3VS ITP_TCK ITP_TRST# 0.1U_0402_16V4Z R9 R9 R10 R10 CPU THERMAL SENSOR 1 C75 C75 U2 U2 2 1 VDD SMCLK 8 EC_SMB_CK2 H_THERMDA 2 DP SMDATA 7 EC_SMB_DA2 H_THERMDC 2200P_0402_50V7K 3 DN ALERT# 6 2 4 THERM# GND 5 C76 C76 1 2 EC_SMB_CK2 <25> EC_SMB_DA2 <25> R52 R52 1 10K_0402_5% +3VS A A EMC1402-1-ACZL-TR_MSOP8 Address:100_1100 2006/08/18 Issued Date Compal Electronics, Inc. Compal Secret Data