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HP Probook 5310M

# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# ADSTB[1]# A20M# FERR# IGNNE# <5,20> H_PWRGOOD R10 51_0402_1% P C7 D4 F10 H_DEFER# <8> H_DRDY# <8> H_DBSY# <8> G <20> H_A20M# <20> H_FERR# <20> H_IGNNE# N5 F38 J1 RESET# RS[0]# RS[1]# RS[2]# TRDY# REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]# ICH <8> H_ADSTB#1 AN1 AK4 AG1 AT4 AK2 AT2 AH2 AF4 AJ5 AH4 AM4 AP4 AR5 AJ1 AL1 AM2 AU5 AP2 AR1 AN5 H_ADS# <8> H_BNR# <8> H_BPRI# <8> LOCK# ADDR GROUP 1 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 C DEFER# DRDY# DBSY# M4 J5 L5 3 R1 R5 U1 P4 W5 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 ADS# BNR# BPRI# PAD 2 <8> <8> <8> <8> <8> <8> H_A#[17..35] A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]# TP19 1 <8> H_ADSTB#0 P2 V4 W1 T4 AA1 AB4 T2 AC5 AD2 AD4 AA5 AE5 AB2 AC1 Y4 ADDR GROUP 0 H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 R8 1K_0402_5% 2 1 H_PWRGOOD_R 02/03 install-->@ 2 H_A#[3..16] XDP/ITP SIGNALS <8> D 2 Title Compal Electronics, Inc. Penryn(1/3)-AGTL+/ITP-XDP Size Document Number Custom LA-5221P Date: R ev 0.1 Tuesday, February 03, 2009 Sheet 1 4 of 45 4 3 2 1 +VCC_CORE  A37 C37 B38 <15> CPU_BSEL0 <15> CPU_BSEL1 <15> CPU_BSEL2 GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 DATA GROUP 2 COMP[0] MISC COMP[1] BSEL[0] BSEL[1] BSEL[2] COMP[2] COMP[3] DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI# H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DSTBN#3 H_DSTBP#3 H_DINV#3 AE43 AD44 AE1 AF2 COMP0 COMP1 COMP2 COMP3 G7 B8 C41 E7 D10 BD10 H_DSTBN#2 <8> H_DSTBP#2 <8> H_DINV#2 <8> H_D#[48..63] <8> H_DSTBN#3 <8> H_DSTBP#3 <8> H_DINV#3 <8> H_DPRSTP# <8,20,42> H_DPSLP# <20> H_DPWR# <8> H_PWRGOOD <4,20> H_CPUSLP# <8> PENRYN SFF_UFCBGA956 ULV723@ layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs CPU_BSEL B 166 CPU_BSEL2 CPU_BSEL1 0 1 Cause CPU core power change to 1 phase, and not need support the pin, leave it as TP. 10/02 12/22 HP review Remove test point CPU_BSEL0 1 200 0 1 0 0 VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100] VCCP_001 VCCP_002 VCCP_003 VCCP_004 VCCP_005 VCCP_006 VCCP_007 VCCP_008 VCCP_009 VCCP_010 VCCP_011 VCCP_012 VCCP_013 VCCP_014 VCCP_015 VCCP_016 VCCA[01] VCCA[02] VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] VCCSENSE VSSSENSE D 12/22 HP review Remove 0 ohm +VCCP J11 E11 G11 J37 K38 L37 N37 P38 R37 U37 V38 W37 AA37 AB38 AC37 AE37 C 1 + Change to 330u_R9, casue high limitation. 12/14 C6 330U_D2E_2.5VM_R9 2 B34 D34 +1.5VS BD8 BC7 BB10 BB8 BC5 BB4 AY4 CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6 BD12 VCCSENSE BC13 VSSSENSE <42> <42> <42> <42> <42> <42> <42> VCCSENSE <42> 1 C7 2 1 C8 2 Near pin D34 Near pin B34 VSSSENSE <42> B PENRYN SFF_UFCBGA956 Length match within 25 mils. The trace width/space/other is 20/7/25. ULV723@ 0 266 Resistor placed within 0.5" of CPU pin.Trace should be at least 25 mils away from any other toggling signal. COMP[0,2] trace width is 18 mils. COMP[1,3] trace width is 4 mils. VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[01