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Acer Aspire 8730, 8730Z

2->1) CFG20 Digital Display Port (SDVO/DP/iHDMI) Concurrent with PCIe 0 = Only Digital Display Port or PCIE is operational (Default) 1 =Digital display Port and PCIe are operting simulataneously via the PEG port 0 =No SDVO Card Present (Default) SDVO_CTRLDATA SDVO Present 1 = SDVO Card Present 0 = LFP Disabled (Default) L_DDC_DATA Local Flat Panel (LFP) Present 1= LFP Card Present; PCIE disabled NOTE: 1. All strap signals are sampled with respect to the leading edge of the (G)MCH Power OK (PWROK) signal. 2. iTPM can be disabled by a 'Soft-Strap' option in the Flash-decriptor section of the Firmware. This 'Soft-Strap' is activated only after enabling iTPM via CFG6. Only one of the CFG10/CFG/12/CFG13 straps can be enabled at any time. 2 Thermal MXM BAT_SCL BAT_SDA BATTERY Device 0 USB1 1 USB4 2 USB2 3 USB5(DOCK) 4 USB3 5 Bluetooth 6 FP 7 MINIC1 Wistron Corporation 8 WEBCAM 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 9 NEW1 10 MINIC2 11 NC CHARGER SO-DIMM ICH9M UMA 1 Title SMBC_ICH 9LPRS365BKLFT DDR Size A3 Reference Document Number Rev -1 Big Bear 2 Date: Wednesday, October 22, 2008 Sheet 2 of 50 B C D 3D3V_S0 3 27 20 CLK48_CR CLK48_ICH GEN_XTAL_OUT 2 1 CPU_SEL0 R221 2 3 2 RN46 CLK48 8 7 6 5 1 2 3 4 PCLKCLK2 PCLKCLK4 PCLKCLK5 CPU_SEL2_R 2 R228 DY RN48 CPU_SEL2 37 36 20 20 CLK48_CR 1 2 3 4 PCLK_FWH PCLK_KBC PCLK_ICH CLK_ICH14 8 7 6 5 CPU_SEL1 CPU_SEL2_R CLK_PWRGD 64 5 55 1 1 1 1 1 1 2 2 2 2 2 19 27 43 52 33 56 VDD96_IO VDDPLL3_IO VDDSRC_IO VDDSRC_IO VDDSRC_IO VDDCPU_IO New Card CLK_PCIE_MINI1 32 CLK_PCIE_MINI1# 32 41 42 CLK_PCIE_LAN 28 CLK_PCIE_LAN# 28 LAN 40 39 37 38 CLK_PCIE_PEG 30 CLK_PCIE_PEG# 30 MXM 34 35 CLK_MCH_3GPLL 7 CLK_MCH_3GPLL# 7 NB CLK 31 32 CLK_PCIE_MINI2 32 CLK_PCIE_MINI2# 32 TV 28 29 CLK_PCIE_SATA 19 CLK_PCIE_SATA# 19 SB SATA 2 1 3 4 RN44 SRN0J-6-GP DREFSSCLK 7 DREFSSCLK# 7 SRCT0/DOTT_96 SRCC0/DOTC_96 20 21 DREFCLK_1 DREFCLK#_1 2 1 3 4 RN45 SRN0J-6-GP DREFCLK 7 DREFCLK# 7 ICS9LPRS365BKLFT-GP-U ICS9LPRS365BKLFT setting table PIN NAME DESCRIPTION 71.09365.A03 71.00875.C03 RTM875N-606-VD-GRT-GP PCI0/CR#_A PCI1/CR#_B PCI2/TME 0 = Overclocking of CPU and SRC Allowed 1 = Overclocking of CPU and SRC NOT allowed PCI3 3.3V PCI clock output PCI4/27M_SEL 0 = Pin24 as SRC-1, Pin25 as SRC-1#, Pin20 as DOT96, Pin21 as DOT96# 1 = Pin24 as 27MHz, Pin25 as 27MHz_SS, Pin20 as SRC-0, Pin21 as SRC-0# PCI_F5/ITP_EN 0 =SRC8/SRC8# 1 = ITP/ITP# SRCT3/CR#_C Byte 5, bit 3 0 = SRC3 enabled (default) 1= CR#_C enabled. Byte 5, bit 2 controls whether CR#_C controls SRC0 or SRC2 pair Byte 5, bit 2 0 = CR#_C controls SRC0 pair (default), 1= CR#_C controls SRC2 pair UMA Byte 5, bit 7 0 = PCI0 enabled (default) 1= CR#_A enabled. Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair Byte 5, bit 6 0 = CR#_A controls SRC0 pair (default), 1= CR#_A controls SRC2 pair Byte 5, bit 5 0 = PCI1 enabled (default) 1= CR#_B enabled. Byte 5, bit 6 controls whether CR#_B controls SRC1 or SRC4 pair Byte 5, bit 4 0 = CR#_B controls SRC1 pair (default) 1= CR#_B controls SRC4 pair GND DY SEL2 SEL1 SEL0 FSC FSB FSA PIN NAME DESCRIPTION SRCC3/CR#_D Byte 5, bit 1 0 = SRC3 enabled (default) 1= CR#_D enabled. Byte 5, bit 0 controls whether CR#_D controls SRC1 or SRC4 pair Byte 5, bit 0 0 = CR#_D controls SRC1 pair (default) 1= CR#_D controls SRC4 pair SRCC7/CR#_E Byte 6, bit 7 0 = SRC7# enabled (default) 1= CR#_F controls SRC6 SRCT7/CR#_F Byte 6, bit 6 0 = SRC7