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Acer Aspire 5935G

_0402_10V6K 2 C50 0.1U_0402_10V6K FOX_PZ4782A-274M-41_Merom . CONN@ A A 2007/09/29 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2007/09/29 Deciphered Date Title SCHEMATIC,MB A5011 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev B 401673 Date: 5 4 3 2 Sheet Thursday, April 30, 2009 1 6 of 43 2 1 2 (4) (4) (4) PM_EXTTS#0_1 PLT_RST# 1 R41 2 1 2 1 1 Near B3 pin R63 R63 1K_0402_5% 1@ C55 BG48 BF48 BD48 BC48 BH47 BG47 BE47 BH46 BF46 BG45 BH44 BH43 BH6 BH5 BG4 BH3 BF3 BH2 BG2 BE2 BG1 BF1 BD1 BC1 F1 A47 NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16 NC_17 NC_18 NC_19 NC_20 NC_21 NC_22 NC_23 NC_24 NC_25 NC_26 2 1 2 1 2 330_0402_5% 2 B E Q5 MMBT3904_SOT23-3 <BOM Structure> DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS2_DIMMB# DDR_CS3_DIMMB# SA_ODT_0 SA_ODT_1 SB_ODT_0 SB_ODT_1 BD17 AY17 BF15 AY13 M_ODT0 M_ODT1 M_ODT2 M_ODT3 SM_RCOMP SM_RCOMP# BG22 BH21 SMRCOMP SMRCOMP# SM_RCOMP_VOH SM_RCOMP_VOL BF28 BH28 SMRCOMP_VOH SMRCOMP_VOL SM_VREF SM_PWROK SM_REXT SM_DRAMRST# AV42 AR36 BF17 BC36 +V_DDR3_MCH_REF SM_PWROK SM_REXT R37 SM_DRAMRST# B38 A38 E41 F41 CLK_MCH_DREFCLK CLK_MCH_DREFCLK# MCH_SSCDREFCLK MCH_SSCDREFCLK# F43 E43 CLK_MCH_3GPLL CLK_MCH_3GPLL# AE41 AE37 AE47 AH39 DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 AE40 AE38 AE48 AH40 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 AE35 AE43 AE46 AH42 DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3 AD35 AE44 AF46 AH43 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3 GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4 B33 B32 G33 F33 E33 GFX_VR_EN C34 PEG_CLK PEG_CLK# M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3 (13) (13) (14) (14) DDR_CKE0_DIMMA DDR_CKE1_DIMMA DDR_CKE2_DIMMB DDR_CKE3_DIMMB (13) (13) (14) (14) DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS2_DIMMB# DDR_CS3_DIMMB# (13) (13) (14) (14) M_ODT0 M_ODT1 M_ODT2 M_ODT3 R34 R35 D (13) (13) (14) (14) +1.5V 2 80.6_0402_1% 2 80.6_0402_1% 1 1 DDR3 DDR3 R1101 1 0_0402_5% 2 DDR3_SM_PWROK (30,39) 1 2 499_0402_1% SM_DRAMRST# (13,14) CLK_MCH_DREFCLK (15) CLK_MCH_DREFCLK# (15) MCH_SSCDREFCLK (15) MCH_SSCDREFCLK# (15) CLK_MCH_3GPLL (15) CLK_MCH_3GPLL# (15) C (18,41) CL_CLK CL_DATA CL_PWROK CL_RST# CL_VREF AH37 AH36 AN36 AJ35 AH34 DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 (18) (18) (18) (18) DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 (18) (18) (18) (18) DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 (18) (18) (18) (18) DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3 (18) (18) (18) (18) VGATE 1 R55 ICH_PWROK 1 R66 VGATE (18) ICH_PWROK GMCH_PWROK 2 @ 0_0402_5% 2 0_0402_5% B +VCCP CL_CLK0 CL_DATA0 1 2 R51 CL_RST# 0_0402_5% CL_VREF DDPC_CTRLCLK DDPC_CTRLDATA SDVO_CTRLCLK SDVO_CTRLDATA CLKREQ# ICH_SYNC# N28 M28 G36 E36 K36 H36 SDVO_SCLK SDVO_SDAT CLKREQ#_7 MCH_ICH_SYNC# TSATN# B12 CL_CLK0 (18) CL_DATA0 (18) R42 1K_0402_1% ICH_PWROK CL_RST# (18) HDA_BCLK HDA_RST# HDA_SDI HDA_SDO HDA_SYNC B28 B30 B29 C29 A28 C56 0.1U_0402_16V4Z 1 511_0402_1% R43 MCH_TSATN# T36 T37 SDVO_SCLK (21) SDVO_SDAT (21) CLKREQ#_7 (15) MCH_ICH_SYNC# 2 (18) 33_0402_5% UMA@ R109 HDA_BITCLK_MCH HDA_RST_MCH# HDA_SDIN1_MCH 1 HDA_SDOUT_MCH HDA_SYNC_MCH HDA_BITCLK_MCH (17) HDA_RST_MCH# (17) 2 HDA_SDIN1 (17) HDA_SDOUT_MCH (17) HDA_SYNC_MCH (17) A 2007/09/29 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification C BA17 AY16 AV16 AR13 (13) (13) (14) (14) CANTIGA_1p0 MCH_TSATN_EC# (31) R68 R68 MCH_TSATN# normal:low over temp:high 2 R64 R64 54.9_0402_1% SA_CS#_0 SA_CS#_1 SB_CS#_0 SB_CS#_1 DMI PM_SYNC# PM_DPRSTP# PM_EXT_TS#_0 PM_EXT_TS#_1 PWROK RSTIN# THERMTRIP# DPRSLPVR R47 1K_0402_1% C57 DDR_CKE0_DIMMA DDR_CKE1_DIMMA DDR_CKE2_DIMMB DDR_CKE3_DIMMB CLK R29 B7 N33 P32 AT40 AT11 T20 R32 +3VS 3 C59 change logic define by EC DDR3 R44 1K_0402_1% 0.1U_0402_16V4Z H_SWNG R67 1 1 2 R520 100_0402_5% 2 0_0402_5% +1.5V R46 1 PM_BMBUSY# H_DPRSTP# PM_EXTTS#0 2 0_0402_5% GMCH_PWROK PLT_RST#_NB THERMTRIP# DPRSLPVR (18) PM_BMBUSY# H_DPRSTP# +V_DDR3_MCH_REF R54 R54 CFG19 CFG20 2 4.02K_0402_1% @ T89 1 R1843 ME H_RS#0 H_RS#1 H_RS#2 CFG16 T86 +3VS (13,14) PM_EXTTS#0_1 +VCCP within 100 mils from NB C54 (4) (4) (4) (4) (4) MISC H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 CFG12 CFG13 T82 T83 Layout Note: V_DDR_MCH_REF trace width and spacing is 20/20. 0.1U_0402_16V4Z 221_0603_1%