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BENQ Joybook U102

S80 VSS81 VSS82 VSS83 VSS84 1 2 U19D A2 A4 A8 A15 A18 A19 A20 B1 B2 B5 B8 B13 B20 B21 C8 C17 D1 D5 D8 D14 D18 D21 E3 E6 E7 E8 E15 E16 E19 F4 F5 F6 F7 F17 F18 G1 G4 G7 G9 G13 G21 H3 H4 H7 H9 H13 H16 H18 H19 J5 J7 J9 J13 J17 K1 K6 K7 K9 K13 K15 K21 L3 L4 L5 L6 L7 L9 L13 L15 L18 L19 M1 M5 M7 M9 M13 M21 N4 2 1 2 C26 C26 2 10U_0805_6.3V6M 1 C56 C56 2 10U_0805_6.3V6M 2 2 1U_0402_6.3V6K 1 2 C55 C55 10U_0805_6.3V6M 1 C344 C344 2 10U_0805_6.3V6M 2 1U_0402_6.3V6K 1 C58 C58 2 2 2 1U_0402_6.3V6K 2 10U_0805_6.3V6M 1 C57 C57 2 1 C24 C24 2 10U_0805_6.3V6M 2 1U_0402_6.3V6K 2 2 1U_0402_6.3V6K 2 2 1U_0402_6.3V6K 10U_0805_6.3V6M 1 C342 C342 2 1 C27 C27 2 10U_0805_6.3V6M 12/29 Remove C331-->330U 1 2 A 10U_0805_6.3V6M PLACE IN CORRIDOR AND CLOSE TO CPU Compal Electronics, Inc. Compal Secret Data Security Classification 2006/08/18 Issued Date Deciphered Date 2008/09/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Diamondville(2/2) Size B Date: Document Number Rev 1.0 KTV00 LA-5241P Thursday, May 07, 2009 Sheet 1 5 of 39 5 4 3 2 1 0211 Add C427, C428, C429 for power noise Change C427 from 100p to 330p 0319 Change C428 C429 from 100p to 220p 0319 MCH_CLKSEL0 <4> H_XRCOMP H_XSCOMP H_XSWING H_YRCOMP H_YSCOMP H_YSWING H_D#[32..47] C <4> H_D#[48..63] R297 R297 54.9_0402_1% 2 1 R311 R311 54.9_0402_1% 2 1 +VCCP R306 R306 24.9_0402_1% 2 1 R298 R298 24.9_0402_1% 2 1 B H_ADS# H_ADSTB#_0 H_ADSTB#_1 H_VREF0 H_BNR# H_BPRI# H_BREQ0# H_CPURST# H_VREF1 F10 C12 H16 E2 B9 C7 G8 B10 E1 H_ADS# H_ADSTB#0 H_ADSTB#1 +H_VREF H_BNR# H_BPRI# H_BR0# H_RESET# +H_VREF HCLKN HCLKP H_DBSY# H_DEFER# H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3 H_DPWR# H_DRDY# H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3 H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3 AA6 AA5 C10 C6 H5 J6 T9 U6 G7 E6 F3 M8 T1 AA3 F4 M7 T2 AB3 CLK_MCH_BCLK# CLK_MCH_BCLK H_DBSY# H_DEFER# H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 H_DPWR# H_DRDY# H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 H_HIT# H_HITM# H_LOCK# H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4 H_RS#_0 H_RS#_1 H_RS#_2 H_SLPCPU# H_TRDY# C8 B4 C5 G9 E9 G12 B8 F12 A5 B6 G10 E8 E10 H_HIT# H_HITM# H_LOCK# H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_RS#0 H_RS#1 H_RS#2 H_CPUSLP# H_TRDY# 2 U18B C427 C427 330P_0402_50V7K <17> <17> <17> <17> C427 close to U18 <17> <17> <17> <17> MCH_CLKSEL1 1 H_A#[17..31] <4> 2 C428 C428 220P_0402_50V7K DMI_TXN0 DMI_TXN1 DMI_TXP0 DMI_TXP1 DMI_RXN0 DMI_RXN1 DMI_RXP0 DMI_RXP1 Y29 Y32 Y28 Y31 DMI_RXN_0 DMI_RXN_1 DMI_RXP_0 DMI_RXP_1 DMI_RXN0 DMI_RXN1 DMI_RXP0 DMI_RXP1 DMI_TXN0 DMI_TXN1 DMI_TXP0 DMI_TXP1 V28 V31 V29 V32 DMI_TXN_0 DMI_TXN_1 DMI_TXP_0 DMI_TXP_1 M_CLK_DDR0 M_CLK_DDR1 MCH_CLKSEL2 1 2 M_CLK_DDR#0 M_CLK_DDR#1 <11> M_CLK_DDR#0 <11> M_CLK_DDR#1 C429 C429 220P_0402_50V7K DDR_CKE0 DDR_CKE1 <11> DDR_CKE0 <11> DDR_CKE1 C429 close to U12 SM_CK_2 SM_CK_3 AG33 AF1 SM_CK#_0 SM_CK#_1 SM_CK#_2 SM_CK#_3 AN21 AN22 AF26 AF25 SM_CKE_0 SM_CKE_1 SM_CKE_2 SM_CKE_3 AG14 AF12 AK14 AH12 SM_CS#_0 SM_CS#_1 SM_CS#_2 SM_CS#_3 AJ21 AF11 H_BNR# <4> H_BPRI# <4> H_BR0# <4> H_RESET# <4> CLK_MCH_BCLK# <12> CLK_MCH_BCLK <12> H_DBSY# <4> H_DEFER# <4> H_DINV#0 <4> H_DINV#1 <4> H_DINV#2 <4> H_DINV#3 <4> H_DPWR# <4> H_DRDY# <4> H_DSTBN#0 <4> H_DSTBN#1 <4> H_DSTBN#2 <4> H_DSTBN#3 <4> H_DSTBP#0 <4> H_DSTBP#1 <4&g