Платформа установлена в:

BENQ Joybook U102

SE SLB2R A3_FCBGA998 Strap Pin Table CFG5 Layout Note: H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 / H_SWNG1 trace width and spacing is 10/20. +VCCP Low = DMI x 2 * High = DMI x 4 +VCCP 1 R20 R20 +H_SWNG0 221_0402_1% 2 1 2 R1 R1 100_0402_1% 221_0402_1% +3VS PM_EXTTS#0 PM_EXTTS#1 1 R17 R17 1 R25 @ 2 10K_0402_5% 2 10K_0402_5% A +H_SWNG1 1 2 0.1U_0402_16V4Z C12 C12 1 R19 R19 2 2 100_0402_1% 1 0.1U_0402_16V4Z C4 C4 1 2 2 C50 be placed <100mils from GMCH pin 100_0402_1% 1 R3 R3 C11 C11 +H_VREF 0.1U_0402_16V4Z 2 R15 R15 1 2 A 200_0402_1% R16 R16 1 +VCCP 2006/08/18 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2008/09/20 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Calistoga(1/5)-GTL/DMI/DDR Size Document Number Custom Date: Rev 1.0 KTV00 LA-5241P Sheet Thursday, May 07, 2009 1 6 of 39 5 4 3 2 U18C D DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 SA_BS_0 SA_BS_1 SA_BS_2 AB30 AL31 AF30 AK26 AL9 AG7 AK5 AH3 SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7 DDR_A_DQS0 AC28 DDR_A_DQS1 AJ30 DDR_A_DQS2 AK33 DDR_A_DQS3 AL25 DDR_A_DQS4 AN9 DDR_A_DQS5 AH8 DDR_A_DQS6 AM2 DDR_A_DQS7 AE3 DDR_A_DQS#0 AC29 DDR_A_DQS#1 AK30 DDR_A_DQS#2 AJ33 DDR_A_DQS#3 AM25 DDR_A_DQS#4 AN8 DDR_A_DQS#5 AJ8 DDR_A_DQS#6 AM3 DDR_A_DQS#7 AE2 C <11> DDR_A_MA[0..13] SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 DDR_A_CAS# DDR_A_RAS# SA_RCVENIN# SA_RCVENOUT# DDR_A_WE# B SA_CAS# SA_RAS# SA_RCVENIN# SA_RCVENOUT# SA_WE# SB_BS_0 SB_BS_1 SB_BS_2 AN20 AL21 AK21 AK22 AL22 AH22 AG22 AF21 AM21 AE21 AL20 AE22 AE26 AE20 <11> DDR_A_WE# @ T10 PAD @ T9 PAD AJ17 AK18 AN28 AM28 AH17 AH21 AJ20 AE27 <11> DDR_A_CAS# <11> DDR_A_RAS# SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63 AC31 AB28 AE33 AF32 AC33 AB32 AB31 AE31 AH31 AK31 AL28 AK27 AH30 AL32 AJ28 AJ27 AH32 AF31 AH27 AF28 AJ32 AG31 AG28 AG27 AN27 AM26 AJ26 AJ25 AL27 AN26 AH25 AG26 AM12 AL11 AH9 AK9 AM11 AK11 AM8 AK8 AG9 AF9 AF8 AK6 AF7 AG11 AJ6 AH6 AN6 AM6 AK3 AL2 AM5 AL5 AJ3 AJ2 AG2 AF3 AE7 AF6 AH5 AG3 AG5 AF5 SB_CAS# SB_RAS# SB_WE# SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7 DDR_A_MA0 AJ15 DDR_A_MA1 AM17 DDR_A_MA2 AM15 DDR_A_MA3 AH15 DDR_A_MA4 AK15 DDR_A_MA5 AN15 DDR_A_MA6 AJ18 DDR_A_MA7 AF19 DDR_A_MA8 AN17 DDR_A_MA9 AL17 DDR_A_MA10 AG16 DDR_A_MA11 AL18 DDR_A_MA12 AG18 DDR_A_MA13 AL14 <11> DDR_A_DQS#[0..7] SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7 DDR2 DDR2 SYSTEM MEMORY <11> DDR_A_DQS[0..7] AK12 AH11 AG17 DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7 <11> DDR_A_BS0 <11> DDR_A_BS1 <11> DDR_A_BS2 <11> DDR_A_DM[0..7] DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR