Platform is installed in:

Fujitsu-Siemens Amilo Pi1505

as short as possible +1.8VS R97 R301 R312 *40.2R_1% *40.2R_1% 80.6R_1% M_RCOMPN M_RCOMPP R302 80.6R_1% MUXING MB_ODT3 MB_ODT2 MA_ODT1 MA_ODT0 M_OCDCOMP1 M_OCDCOMP0 150R_1% DDR C69 M_RCOMPP M_RCOMPN RSVD_13 RSVD_12 RSVD_11 RSVD_10 RSVD_9 RSVD_8 RSVD_7 RSVD_6 RSVD_5 RSVD_4 RSVD_3 RSVD_2 RSVD_1 RSVD 0.05A C AK41 AK1 CFG M_VREF_MCH GCLK => PCI-E & DMI (100MHZ) DREFCLK => Dispaly PLLA ( nun- ss 96MHZ) DRESSFCLK => Display LVDS PLLB ( ss 100MHZ) SDVODATA has internal pull down 0= no DVO device 1= DVO device present SDVOCLK has internal pull down . D Asserted to control the raw PCI-E clock H32 K28 H27 H28 Z0901 AH34 AH33 G6 H26 F25 G28 GMCH_RST# R95 DELAY_VR_PWRGOOD GMCH_THRMTRIP# R391 PM_EXTTS#1 R171 0R PM_EXTTS#0 R166 0R R173 *0R Add to GMCH_CLK_REQ# 7 GMCH NB_SYNC# 16 check list ( Bat life ) PWROK Asserted to synchronize with ICH on fault 100R PLT_RST# 16,17,20,21,23 DELAY_VR_PWRGOOD 16 PM_THRMTRIP# 5,15 C4_OUT# 21 EXTTS#0 14,21 BM_BUSY# 16 *0R PWROK input level PM_THRMTRIP# space 2:1 Break event in C3 state. GHCH integrated graphics busy CFG_20 CFG_19 CFG_18 CFG_17 CFG_16 CFG_15 CFG_14 CFG_13 CFG_12 CFG_11 CFG_10 CFG_9 CFG_8 CFG_7 CFG_6 CFG_5 CFG_4 CFG_3 CFG_2 CFG_1 CFG_0 R349 150R_1% A3 A39 A4 A40 AW1 AW41 AY1 AY41 B2 B41 BA1 BA2 BA3 BA39 BA40 BA41 C1 C41 D1 J26 K27 J25 H15 G18 H16 C15 K15 G15 D15 E16 G16 D16 D19 E18 F15 E15 F18 J18 K18 K16 RB->M2 CFG19 CFG18 CFG16 Z0902 Z0903 D27 D28 A34 A35 A41 J19 H7 AF11 AG11 F7 F3 R32 T32 13 13 13 PM_THRMTRIP# C R137 R144 *1K *1K C441 0.1u CFG9 13 CFG5 13 CPU_BSEL2 5 CPU_BSEL1 5,21 CPU_BSEL0 5 Base on PWROK Colse to NB DELAY_VR_PWRGOOD C72 0.1u SM_CKE_2(#) connected to Dimm1 CK1(#) SM_CKE_3(#) connected to Dimm1 CK0(#) B B CALISTOGA Only Base on Discreted VGA VCCA_DPLLA , VCCA_DPLLB => NC DREF_CLKP / DREF_SSCLKP = GND DREF_CLKN / DREF_SSCLKN = GND VCCA_DPLLA , VCCA_DPLLB =>1.5V DREF_CLKP / DREF_SSCLKP = 1.5V DREF_CLKN / DREF_SSCLKN = GND CFG0 CFG1 CFG2 Host Clock frequency For MEN bus throttling GRATIS - FOR FREE 1 0 0 133 +3.3V A 1 1 0 166 R156 10K 1= Mobility CPU 0 = Reverse A 10K R150 CFG7 ( IPU ) => PM_EXTTS#0 Name of Part PM_EXTTS#1 Project Check with S/W NB(2)_DMI/VGA/MICS L50II0 Rev C Sheet Date: Tuesday, April 25, 2006 3255 5 4 3 2 9 / 33 UNIWILL COMPUTER CORP. 1 5 4 3 2 1 D D +1.5V R147 24.9R_1% U14C Z1001 LA_DATA#_0 LA_DATA#_1 LA_DATA#_2 B37 B34 A36 LA_DATA_0 LA_DATA_1 LA_DATA_2 22 LVDSB_N0 22 LVDSB_N1 22 LVDSB_N2 G30 D30 F29 LB_DATA#_0 LB_DATA#_1 LB_DATA#_2 22 LVDSB_P0 22 LVDSB_P1 22 LVDSB_P2 F30 D29 F28 LB_DATA_0 LB_DATA_1 LB_DATA_2 TV_DACA TV_DACB TV_DACC A16 C18 A19 TV_DACA_OUT TV_DACB_OUT TV_DACC_OUT TVIREF J20 B16 B18 B19 TV_IREF TV_IRTNA TV_IRTNB TV_IRTNC K30 J29 TV_DCONSEL0 TV_DCONSEL1 22 NB_FPVDDEN 22 22 22 22 LVDSA_CLKN LVDSA_CLKP LVDSB_CLKN LVDSB_CLKP C 24 24 TV_DACB TV_DACC R418 R420 R419 150R 150R 150R R168 B 4.99K_1% NB_CRT_BLUE 25 NB_CRT_GREEN 25 NB_CRT_RED R417 R416 R415 150R 150R 150R 25 NB_DCC_CLK 25 NB_DCC_DATA 25 NB_CRT_HSYNC R139 25 NB_CRT_VSYNC R138 GM_CRT_HSYNC 39R GM_CRT_VSYNC 39R NB_CRT_IREF C26 C25 G23 J22 H23 CRT_BLUE CRT_BLUE# CRT_GREEN CRT_GREEN# CRT_RED CRT_RED# CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_IREF CRT_VSYNC VGA E23 D23 NB_CRT_GREEN C22 B22 NB_CRT_RED A21 B21 25 NB_CRT_BLUE R414 255R_1% GRAPHICS C37 B35 A37 22 LVDSA_P0 22 LVDSA_P1 22 LVDSA_P2 2.2K_1% L_IBG PCI-EXPRESS LA_CLK# LA_CLK LB_CLK# LB_CLK Z1002 Z1003 TV A33 A32 E27 E26 NB_EN_BL 22 NB_LDDC_CLK 22 NB_LDDC_DATA R152 EXP_A_COMPI EXP_A_COMPO L_BKLTCTL L_BKLTEN L_CLKCTLA L_CLKCTLB L_DDC_CLK L_DDC_DATA L_IBG L_VBG L_VDDEN L_VREFH L_VREFL 22 LVDS D32 J30 H30 H29 G26 G25 B38 C35 F32 C33 C32 22 LVDSA_N0 22 LVDSA_N1 22 LVDSA_N2 RC-M2 D40 PEG_COMP D38 EXP_A_RXN_0 EXP_A_RXN_1 EXP_A_RXN_2 EXP_A_RXN_3 EXP_A_RXN_4 EXP_A_RXN_5 EXP_A_RXN_6 EXP_A_RXN_7 EXP_A_RXN_8 EXP_A_RXN_9 EXP_A_RX